The present invention relates to a clocked logic device supplied with a binary signal for issuing the binary signal in synchronism with a clock signal (hereinafter referred to as a "clock") which is in asynchronism with the supplied binary signal.
Where a binary signal is delayed by an analog delay line, for example, the delay is influenced to a greater extent by a change in ambient temperature or the like as the delay time increases. To avoid this drawback, it has been the practice to employ a clocked logic device for delaying a binary signal. The logic circuit has a delay circuit composed for example of n D-type flip-flops (n is an integer of 2 or more) connected in cascade. The first D-type flip-flops is supplied with the binary signal which is successively transferred through the D-type flip-flops by a clock which is in asynchronism with the binary signal, and the final D-type flip-flops issues the binary signal which has been delayed by about (n-1)To (To is the period of the clock). The binary signal delayed by the delay circuit of the logic circuit is less affected by changes in ambient temperature since the signal is delayed by the stable clock.
Since however the input binary signal and the clock are asynchronous with each other in the delay circuit of the logic circuit, the delay of the output binary signal is subjected to an error dependent on the phase difference between the input binary signal and the clock. The error approximates the clock period To at maximum. To reduce this error, the rate of the clock might be increased, but flip-flops operable at a high speed would be expensive and there would be a limitation on increasing the operating speed of the flip-flops. It has therefore been difficult to obtain a delay of high accuracy by using a logic circuit as the delay circuit.
In the case where it is desired to shift the synchronization phase of an output binary signal from a logic oscillation circuit oscillating in synchronism with a clock so that the phase of the oscillation output may coincide with, for example, the rise of an input binary signal which is in asynchronism with the clock, the phase shift can be achieved with high accuracy through the use of the clock of a higher frequency. However, as mentioned previously, such a logic circuit operable at high frequency is expensive.